VLSI Placement and Global Routing Using Simulated Annealing

VLSI Placement and Global Routing Using Simulated Annealing PDF

Author: Carl Sechen

Publisher: Springer Science & Business Media

Published: 2012-12-06

Total Pages: 298

ISBN-13: 1461316979

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From my B.E.E degree at the University of Minnesota and right through my S.M. degree at M.I.T., I had specialized in solid state devices and microelectronics. I made the decision to switch to computer-aided design (CAD) in 1981, only a year or so prior to the introduction of the simulated annealing algorithm by Scott Kirkpatrick, Dan Gelatt, and Mario Vecchi of the IBM Thomas 1. Watson Research Center. Because Prof. Alberto Sangiovanni-Vincentelli, my UC Berkeley advisor, had been a consultant at IBM, I re ceived a copy of the original IBM internal report on simulated annealing approximately the day of its release. Given my background in statistical mechanics and solid state physics, I was immediately impressed by this new combinatorial optimization technique. As Prof. Sangiovanni-Vincentelli had suggested I work in the areas of placement and routing, it was in these realms that I sought to explore this new algorithm. My flJ'St implementation of simulated annealing was for an island-style gate array placement problem. This work is presented in the Appendix of this book. I was quite struck by the effect of a nonzero temperature on what otherwise appears to be a random in terchange algorithm.

VLSI Placement and Routing: The PI Project

VLSI Placement and Routing: The PI Project PDF

Author: Alan T. Sherman

Publisher: Springer Science & Business Media

Published: 2012-12-06

Total Pages: 198

ISBN-13: 1461396581

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This book provides a superb introduction to and overview of the MIT PI System for custom VLSI placement and routing. Alan Sher man has done an excellent job of collecting and clearly presenting material that was previously available only in various theses, confer ence papers, and memoranda. He has provided here a balanced and comprehensive presentation of the key ideas and techniques used in PI, discussing part of his own Ph. D. work (primarily on the place ment problem) in the context of the overall design of PI and the contributions of the many other PI team members. I began the PI Project in 1981 after learning first-hand how dif ficult it is to manually place modules and route interconnections in a custom VLSI chip. In 1980 Adi Shamir, Leonard Adleman, and I designed a custom VLSI chip for performing RSA encryp tion/decryption [226]. I became fascinated with the combinatorial and algorithmic questions arising in placement and routing, and be gan active research in these areas. The PI Project was started in the belief that many of the most interesting research issues would arise during an actual implementation effort, and secondarily in the hope that a practically useful tool might result. The belief was well-founded, but I had underestimated the difficulty of building a large easily-used software tool for a complex domain; the PI soft ware should be considered as a prototype implementation validating the design choices made.

Routing Congestion in VLSI Circuits

Routing Congestion in VLSI Circuits PDF

Author: Prashant Saxena

Publisher: Springer Science & Business Media

Published: 2007-04-27

Total Pages: 254

ISBN-13: 0387485503

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This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

VLSI Physical Design: From Graph Partitioning to Timing Closure

VLSI Physical Design: From Graph Partitioning to Timing Closure PDF

Author: Andrew B. Kahng

Publisher: Springer Nature

Published: 2022-06-14

Total Pages: 329

ISBN-13: 3030964159

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The complexity of modern chip design requires extensive use of specialized software throughout the process. To achieve the best results, a user of this software needs a high-level understanding of the underlying mathematical models and algorithms. In addition, a developer of such software must have a keen understanding of relevant computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. This book introduces and compares the fundamental algorithms that are used during the IC physical design phase, wherein a geometric chip layout is produced starting from an abstract circuit design. This updated second edition includes recent advancements in the state-of-the-art of physical design, and builds upon foundational coverage of essential and fundamental techniques. Numerous examples and tasks with solutions increase the clarity of presentation and facilitate deeper understanding. A comprehensive set of slides is available on the Internet for each chapter, simplifying use of the book in instructional settings. “This improved, second edition of the book will continue to serve the EDA and design community well. It is a foundational text and reference for the next generation of professionals who will be called on to continue the advancement of our chip design tools and design the most advanced micro-electronics.” Dr. Leon Stok, Vice President, Electronic Design Automation, IBM Systems Group “This is the book I wish I had when I taught EDA in the past, and the one I’m using from now on.” Dr. Louis K. Scheffer, Howard Hughes Medical Institute “I would happily use this book when teaching Physical Design. I know of no other work that’s as comprehensive and up-to-date, with algorithmic focus and clear pseudocode for the key algorithms. The book is beautifully designed!” Prof. John P. Hayes, University of Michigan “The entire field of electronic design automation owes the authors a great debt for providing a single coherent source on physical design that is clear and tutorial in nature, while providing details on key state-of-the-art topics such as timing closure.” Prof. Kurt Keutzer, University of California, Berkeley “An excellent balance of the basics and more advanced concepts, presented by top experts in the field.” Prof. Sachin Sapatnekar, University of Minnesota

Field Programmable Logic and Applications

Field Programmable Logic and Applications PDF

Author: Wayne Luk

Publisher: Springer Science & Business Media

Published: 1997-08-20

Total Pages: 66

ISBN-13: 9783540634652

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This book constitutes the refereed proceedings of the 7th International Workshop on Field Programmable Logic and Applications, FPL '97, held in London, UK, in September 1997. The 51 revised full papers in the volume were carefully selected from a large number of high-quality papers. The book is divided into sections on devices and architectures, devices and systems, reconfiguration, design tools, custom computing and codesign, signal processing, image and video processing, sensors and graphics, color and robotics, and applications.

Parallel Algorithms for Placement and Routing in VLSI Design

Parallel Algorithms for Placement and Routing in VLSI Design PDF

Author: Randall Jay Brouwer

Publisher:

Published: 1991

Total Pages: 194

ISBN-13:

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The computational requirements for high quality synthesis, analysis, and verification of VLSI designs have rapidly increased with the fast growing complexity of these designs. Past research has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. In this thesis, we propose two new parallel algorithms for two VLSl synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, we present results which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs, and we present measurements on the parallel speedups available.

Logic Synthesis

Logic Synthesis PDF

Author: Srinivas Devadas

Publisher: McGraw-Hill Professional Publishing

Published: 1994

Total Pages: 0

ISBN-13: 9780070165007

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Logic synthesis enables VSLI designers to rapidly lay out the millions of transistors and interconnecting wires that form the circuitry on modern chips, without having to plot each individual logic circuit.

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