Routing Congestion in VLSI Circuits

Routing Congestion in VLSI Circuits PDF

Author: Prashant Saxena

Publisher: Springer Science & Business Media

Published: 2007-04-27

Total Pages: 254

ISBN-13: 0387485503

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This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

Routing Congestion in VLSI Circuits

Routing Congestion in VLSI Circuits PDF

Author: Prashant Saxena

Publisher: Springer

Published: 2008-11-01

Total Pages: 250

ISBN-13: 9780387510613

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This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

Routing Congestion Analysis and Reduction in Deep Sub-micron VLSI Design

Routing Congestion Analysis and Reduction in Deep Sub-micron VLSI Design PDF

Author: Zion Cien Shen

Publisher:

Published: 2004

Total Pages: 264

ISBN-13:

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Congestion is one of the main optimization objectives in global routing; however, the optimization performance is constrained because the cells are already fixed at this stage. Therefore, a designer can save substantial time and resources by detecting and reducing congested regions during the planning stages. An efficient yet accurate congestion estimation model is crucial to be included in the inner loop of floorplanning and placement design. In this dissertation, we mainly focus on routing congestion modeling and reduction during floorplanning and placement.

Handbook of Algorithms for Physical Design Automation

Handbook of Algorithms for Physical Design Automation PDF

Author: Charles J. Alpert

Publisher: CRC Press

Published: 2008-11-12

Total Pages: 1044

ISBN-13: 1000654192

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The physical design flow of any project depends upon the size of the design, the technology, the number of designers, the clock frequency, and the time to do the design. As technology advances and design-styles change, physical design flows are constantly reinvented as traditional phases are removed and new ones are added to accommodate changes in

Rethinking Global Routing for Modern VLSI Design

Rethinking Global Routing for Modern VLSI Design PDF

Author:

Publisher:

Published: 2012

Total Pages: 0

ISBN-13:

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RETHINKING GLOBAL ROUTING FOR MODERN VLSI DESIGN: CONGESTION REDUCTION AND MULTI-OBJECTIVE OPTIMIZATION Hamid Shojaei Under the supervision of Professor Azadeh Davoodi At the University of Wisconsin-Madison The high volume and complexity of cells and interconnect structures are causing serious challenges to routability in modern VLSI design. Several new factors contribute to routing congestion including significantly-different wire size and spacing among the metal layers, sizes of inter-layer vias, various forms of routing blockages, local congestion due to pin density and wiring inside a global-cell, and virtual pins located at the higher metal layers. In addition, interconnects now play a significant role in impacting the performance metrics of a design including power, speed and area. Global routing, as the first stage in which the interconnects are planned, is now of significant importance in determining the performance metrics and the routability of the design. However, the standard model of global routing considers minimization of wirelength with a simplified model of routing resources which ignores these objectives and complicating factors. To address the above challenges, this dissertation has three contributions in rethinking global routing for modern VLSI design. First, we present a framework for congestion analysis for quick prediction of the locations of highly-utilized routing regions. The fast framework is suitable for integration in the design flow, for example as an integration within a routability-driven placement procedure. Second, we offer two contributions in order to estimate and manage the congestion caused by local nets which are ignored in a standard model of global routing. It allows optimizing congestion directly within global routing by treating global and detailed routing in a more holistic manner. In addition, many of the above-mentioned factors contributing to congestion are accounted for in our congestion analysis and optimization framework. Finally, we present a procedure for multi-objective global routing which is able to optimize multiple performance metrics beyond wirelength. The framework is a collaborative one which receives as input multiple global routing solutions created by single-objective procedures.

Adaptive Techniques for Dynamic Processor Optimization

Adaptive Techniques for Dynamic Processor Optimization PDF

Author: Alice Wang

Publisher: Springer Science & Business Media

Published: 2008-07-23

Total Pages: 312

ISBN-13: 0387764720

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This book is about various adaptive and dynamic techniques used to optimize processor power and performance. It is based on a very successful forum at ISSCC which focused on Adaptive Techniques. The book looks at the underlying process technology for adaptive designs and then examines different circuits, architecture and software that address the different aspects. The chapters are written by people both in academia and the industry to show the scope of alternative practices.

Modern Circuit Placement

Modern Circuit Placement PDF

Author: Gi-Joon Nam

Publisher: Springer Science & Business Media

Published: 2007-08-26

Total Pages: 330

ISBN-13: 0387687394

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This book covers advanced techniques in modern circuit placement. It details all of most recent placement techniques available in the field and analyzes the optimality of these techniques. Coverage includes all the academic placement tools that competed against one another on the same industrial benchmark circuits at the International Symposium on Physical Design (ISPD), these techniques are also extensively being used in industrial tools as well. The book provides significant amounts of analysis on each technique such as trade-offs between quality-of-results (QoR) and runtime.

Ultra-Low Voltage Nano-Scale Memories

Ultra-Low Voltage Nano-Scale Memories PDF

Author: Kiyoo Itoh

Publisher: Springer Science & Business Media

Published: 2007-09-04

Total Pages: 351

ISBN-13: 0387688536

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Ultra-low voltage large-scale integrated circuits (LSIs) in nano-scale technologies are needed both to meet the needs of a rapidly growing mobile cell phone market and to offset a significant increase in the power dissipation of high-end microprocessor units. The goal of this book is to provide a detailed explanation of the state-of-the-art nanometer and sub-1-V memory LSIs that are playing decisive roles in power conscious systems. Emerging problems between the device, circuit, and system levels are systematically discussed in terms of reliable high-speed operations of memory cells and peripheral logic circuits. The effectiveness of solutions at device and circuit levels is also described at length through clarifying noise components in an array, and even essential differences in ultra-low voltage operations between DRAMs and SRAMs.

SAT-Based Scalable Formal Verification Solutions

SAT-Based Scalable Formal Verification Solutions PDF

Author: Malay Ganai

Publisher: Springer Science & Business Media

Published: 2007-05-26

Total Pages: 338

ISBN-13: 0387691677

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This book provides an engineering insight into how to provide a scalable and robust verification solution with ever increasing design complexity and sizes. It describes SAT-based model checking approaches and gives engineering details on what makes model checking practical. The book brings together the various SAT-based scalable emerging technologies and techniques covered can be synergistically combined into a scalable solution.