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Low Power and Reliable SRAM Memory Cell and Array Design

Author: Koichiro Ishibashi

Publisher: Springer Science & Business Media

Published: 2011-08-18

Total Pages: 154

ISBN-13: 3642195687

Success in the development of recent advanced semiconductor device technologies is due to the success of SRAM memory cells. This book addresses various issues for designing SRAM memory cells for advanced CMOS technology. To study LSI design, SRAM cell design is the best materials subject because issues about variability, leakage and reliability have to be taken into account for the design.

Energy Efficient and Reliable Embedded Nanoscale SRAM Design

Author: Bhupendra Singh Reniwal

Publisher: CRC Press

Published: 2023-11-30

Total Pages: 213

ISBN-13: 1000985156

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This reference text covers a wide spectrum for designing robust embedded memory and peripheral circuitry. It will serve as a useful text for senior undergraduate and graduate students and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. Discusses low-power design methodologies for static random-access memory (SRAM) Covers radiation-hardened SRAM design for aerospace applications Focuses on various reliability issues that are faced by submicron technologies Exhibits more stable memory topologies Nanoscale technologies unveiled significant challenges to the design of energy- efficient and reliable SRAMs. This reference text investigates the impact of process variation, leakage, aging, soft errors and related reliability issues in embedded memory and periphery circuitry. The text adopts a unique way to explain the SRAM bitcell, array design, and analysis of its design parameters to meet the sub-nano-regime challenges for complementary metal-oxide semiconductor devices. It comprehensively covers low- power-design methodologies for SRAM, exhibits more stable memory topologies, and radiation-hardened SRAM design for aerospace applications. Every chapter includes a glossary, highlights, a question bank, and problems. The text will serve as a useful text for senior undergraduate students, graduate students, and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. Discussing comprehensive studies of variability-induced failure mechanism in sense amplifiers and power, delay, and read yield trade-offs, this reference text will serve as a useful text for senior undergraduate, graduate students, and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. It covers the development of robust SRAMs, well suited for low-power multi-core processors for wireless sensors node, battery-operated portable devices, personal health care assistants, and smart Internet of Things applications.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

Author: Andrei Pavlov

Publisher: Springer Science & Business Media

Published: 2008-06-01

Total Pages: 203

ISBN-13: 1402083637

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The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.

A Robust Low Power Static Random Access Memory Cell Design

Author: A. V. Rama Raju Pusapati

Publisher:

Published: 2018

Total Pages: 83

ISBN-13:

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Stability of a Static Random Access Memory (SRAM) cell is an important factor when considering an SRAM cell for any application. The Static Noise Margin (SNM) of a cell, which determines the stability, varies under different operating conditions. Based on the performance of three existing SRAM cell designs, 6T, 8T and 10T, a 10 Transistor SRAM cell is proposed which has good stability and has the advantage of reduced read power when compared to 6T and 8T SRAM cells. The proposed 10T SRAM cell has a single-ended read circuit which improves SNM over the 6T cell. The proposed 10T cell doesn't require a pre-charge circuit and this in-turn improves read power and also reduces the read time since there is no need to pre-charge the bit-line before reading it. The Read SNM and Hold SNM of the proposed cell at a VDD of 1V and at 25°C is 254mV. The measured RSNM, HSNM and Write SNM at temperatures 0°C, 40°C, 80°C and 120°C and also at supply voltages 1V, 0.8V and 0.6V show the design is robust. The Write SNM of the proposed cell at a VDD of 1V and Pull-up Ratio of 1 is 275mV. Finally, a 32-byte memory array is built using the proposed 10T SRAM cell and the read, write times are 149ps and 21.6ps, respectively. The average power consumed by the 32-byte array over a 12ns period is 13.8uW. All the designs are done in the 32nm FinFET technology.

Robust SRAM Designs and Analysis

Author: Jawar Singh

Publisher: Springer Science & Business Media

Published: 2012-08-01

Total Pages: 176

ISBN-13: 1461408180

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This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.

Terrestrial Radiation Effects in ULSI Devices and Electronic Systems

Author: Eishi H. Ibe

Publisher: John Wiley & Sons

Published: 2015-03-02

Total Pages: 292

ISBN-13: 1118479297

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This book provides the reader with knowledge on a wide variety of radiation fields and their effects on the electronic devices and systems. The author covers faults and failures in ULSI devices induced by a wide variety of radiation fields, including electrons, alpha-rays, muons, gamma rays, neutrons and heavy ions. Readers will learn how to make numerical models from physical insights, to determine the kind of mathematical approaches that should be implemented to analyze radiation effects. A wide variety of prediction, detection, characterization and mitigation techniques against soft-errors are reviewed and discussed. The author shows how to model sophisticated radiation effects in condensed matter in order to quantify and control them, and explains how electronic systems including servers and routers are shut down due to environmental radiation. Provides an understanding of how electronic systems are shut down due to environmental radiation by constructing physical models and numerical algorithms Covers both terrestrial and avionic-level conditions Logically presented with each chapter explaining the background physics to the topic followed by various modelling techniques, and chapter summary Written by a widely-recognized authority in soft-errors in electronic devices Code samples available for download from the Companion Website This book is targeted at researchers and graduate students in nuclear and space radiation, semiconductor physics and electron devices, as well as other areas of applied physics modelling. Researchers and students interested in how a variety of physical phenomena can be modelled and numerically treated will also find this book to present helpful methods.

Energy Efficient and Reliable Embedded Nanoscale SRAM Design

Author: Bhupendra Singh Reniwal

Publisher: CRC Press

Published: 2023-11-29

Total Pages: 221

ISBN-13: 100098513X

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CMOS SRAM Memory Chip Design

Author: Sakshi Rajput

Publisher: LAP Lambert Academic Publishing

Published: 2013-01

Total Pages: 136

ISBN-13: 9783659320378

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Static random-access memory (SRAM) continues to be a critical component across a wide range of microelectronics applications from consumer wireless to high-end workstation and microprocessor applications. For almost all fields of applications, semiconductor memory has been a key enabling technology. It is forecasted that embedded memory in SOC designs will cover up to 90% of the total chip area. A representative example is the use of cache memory in microprocessors. The operational speed could be significantly improved by the application of on-chip cache memory Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital systems. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and, consequently, toward higher storage densities. This book deals with design of low power static random-access memory cells and peripheral circuits for standalone RAMs, in 350nm focusing on stable operation and reduced leakage current and power dissipation in standby and active modes.

SRAM Design for Wireless Sensor Networks

Author: Vibhu Sharma

Publisher: Springer Science & Business Media

Published: 2012-07-27

Total Pages: 179

ISBN-13: 1461440394

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This book features various, ultra low energy, variability resilient SRAM circuit design techniques for wireless sensor network applications. Conventional SRAM design targets area efficiency and high performance at the increased cost of energy consumption, making it unsuitable for computation-intensive sensor node applications. This book, therefore, guides the reader through different techniques at the circuit level for reducing energy consumption and increasing the variability resilience. It includes a detailed review of the most efficient circuit design techniques and trade-offs, introduces new memory architecture techniques, sense amplifier circuits and voltage optimization methods for reducing the impact of variability for the advanced technology nodes.

VLSI Design and Test for Systems Dependability

Author: Shojiro Asai

Publisher: Springer

Published: 2018-07-20

Total Pages: 800

ISBN-13: 4431565949

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This book discusses the new roles that the VLSI (very-large-scale integration of semiconductor circuits) is taking for the safe, secure, and dependable design and operation of electronic systems. The book consists of three parts. Part I, as a general introduction to this vital topic, describes how electronic systems are designed and tested with particular emphasis on dependability engineering, where the simultaneous assessment of the detrimental outcome of failures and cost of their containment is made. This section also describes the related research project “Dependable VLSI Systems,” in which the editor and authors of the book were involved for 8 years. Part II addresses various threats to the dependability of VLSIs as key systems components, including time-dependent degradations, variations in device characteristics, ionizing radiation, electromagnetic interference, design errors, and tampering, with discussion of technologies to counter those threats. Part III elaborates on the design and test technologies for dependability in such applications as control of robots and vehicles, data processing, and storage in a cloud environment and heterogeneous wireless telecommunications. This book is intended to be used as a reference for engineers who work on the design and testing of VLSI systems with particular attention to dependability. It can be used as a textbook in graduate courses as well. Readers interested in dependable systems from social and industrial–economic perspectives will also benefit from the discussions in this book.