Design of Low-Power Coarse-Grained Reconfigurable Architectures

Design of Low-Power Coarse-Grained Reconfigurable Architectures PDF

Author: Yoonjin Kim

Publisher: CRC Press

Published: 2010-12-09

Total Pages: 215

ISBN-13: 1439825114

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Coarse-grained reconfigurable architecture (CGRA) has emerged as a solution for flexible, application-specific optimization of embedded systems. Helping you understand the issues involved in designing and constructing embedded systems, Design of Low-Power Coarse-Grained Reconfigurable Architectures offers new frameworks for optimizing the architect

Designing Cost-effective Coarse-grained Reconfigurable Architecture

Designing Cost-effective Coarse-grained Reconfigurable Architecture PDF

Author: Yoonjin Kim

Publisher:

Published: 2010

Total Pages:

ISBN-13:

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Application-specific optimization of embedded systems becomes inevitable to satisfy the market demand for designers to meet tighter constraints on cost, performance and power. On the other hand, the flexibility of a system is also important to accommodate the short time-to-market requirements for embedded systems. To compromise these incompatible demands, coarse-grained reconfigurable architecture (CGRA) has emerged as a suitable solution. A typical CGRA requires many processing elements (PEs) and a configuration cache for reconfiguration of its PE array. However, such a structure consumes significant area and power. Therefore, designing cost-effective CGRA has been a serious concern for reliability of CGRA-based embedded systems. As an effort to provide such cost-effective design, the first half of this work focuses on reducing power in the configuration cache. For power saving in the configuration cache, a low power reconfiguration technique is presented based on reusable context pipelining achieved by merging the concept of context reuse into context pipelining. In addition, we propose dynamic context compression capable of supporting only required bits of the context words set to enable and the redundant bits set to disable. Finally, we provide dynamic context management capable of reducing reduce power consumption in configuration cache by controlling a read/write operation of the redundant context words In the second part of this dissertation, we focus on designing a cost-effective PE array to reduce area and power. For area and power saving in a PE array, we devise a costeffective array fabric addresses novel rearrangement of processing elements and their interconnection designs to reduce area and power consumption. In addition, hierarchical reconfigurable computing arrays are proposed consisting of two reconfigurable computing blocks with two types of communication structure together. The two computing blocks have shared critical resources and such a sharing structure provides efficient communication interface between them with reducing overall area. Based on the proposed design approaches, a CGRA combining the multiple design schemes is shown to verify the synergy effect of the integrated approach. Experimental results show that the integrated approach reduces area by 23.07% and power by up to 72% when compared with the conventional CGRA.

Fine- and Coarse-Grain Reconfigurable Computing

Fine- and Coarse-Grain Reconfigurable Computing PDF

Author: Stamatis Vassiliadis

Publisher: Springer Science & Business Media

Published: 2007-10-12

Total Pages: 389

ISBN-13: 1402065043

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Fine- and Coarse-Grain Reconfigurable Computing gives the basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described. Part I consists of two extensive surveys of FPGA and Coarse-Grain Reconfigurable Architectures. In Part II, case studies, innovative research results about reconfigurable architectures and design frameworks from three projects AMDREL, MOLEN and ADRES and DRESC, and, a new classification according to microcoded architectural criteria are described. Fine- and Coarse-Grain Reconfigurable Computing is an essential reference for researchers and professionals and can be used as a textbook by undergraduate, graduate students and professors.

Low-Power Processors and Systems on Chips

Low-Power Processors and Systems on Chips PDF

Author: Christian Piguet

Publisher: CRC Press

Published: 2018-10-03

Total Pages: 392

ISBN-13: 142003720X

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The power consumption of microprocessors is one of the most important challenges of high-performance chips and portable devices. In chapters drawn from Piguet's recently published Low-Power Electronics Design, this volume addresses the design of low-power microprocessors in deep submicron technologies. It provides a focused reference for specialists involved in systems-on-chips, from low-power microprocessors to DSP cores, reconfigurable processors, memories, ad-hoc networks, and embedded software. Low-Power Processors and Systems on Chips is organized into three broad sections for convenient access. The first section examines the design of digital signal processors for embedded applications and techniques for reducing dynamic and static power at the electrical and system levels. The second part describes several aspects of low-power systems on chips, including hardware and embedded software aspects, efficient data storage, networks-on-chips, and applications such as routing strategies in wireless RF sensing and actuating devices. The final section discusses embedded software issues, including details on compilers, retargetable compilers, and coverification tools. Providing detailed examinations contributed by leading experts, Low-Power Processors and Systems on Chips supplies authoritative information on how to maintain high performance while lowering power consumption in modern processors and SoCs. It is a must-read for anyone designing modern computers or embedded systems.

Handbook of Signal Processing Systems

Handbook of Signal Processing Systems PDF

Author: Shuvra S. Bhattacharyya

Publisher: Springer Science & Business Media

Published: 2010-09-10

Total Pages: 1099

ISBN-13: 1441963456

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It gives me immense pleasure to introduce this timely handbook to the research/- velopment communities in the ?eld of signal processing systems (SPS). This is the ?rst of its kind and represents state-of-the-arts coverage of research in this ?eld. The driving force behind information technologies (IT) hinges critically upon the major advances in both component integration and system integration. The major breakthrough for the former is undoubtedly the invention of IC in the 50’s by Jack S. Kilby, the Nobel Prize Laureate in Physics 2000. In an integrated circuit, all components were made of the same semiconductor material. Beginning with the pocket calculator in 1964, there have been many increasingly complex applications followed. In fact, processing gates and memory storage on a chip have since then grown at an exponential rate, following Moore’s Law. (Moore himself admitted that Moore’s Law had turned out to be more accurate, longer lasting and deeper in impact than he ever imagined. ) With greater device integration, various signal processing systems have been realized for many killer IT applications. Further breakthroughs in computer sciences and Internet technologies have also catalyzed large-scale system integration. All these have led to today’s IT revolution which has profound impacts on our lifestyle and overall prospect of humanity. (It is hard to imagine life today without mobiles or Internets!) The success of SPS requires a well-concerted integrated approach from mul- ple disciplines, such as device, design, and application.

Reconfigurable Computing: Architectures, Tools and Applications

Reconfigurable Computing: Architectures, Tools and Applications PDF

Author: Pedro C. Diniz

Publisher: Springer

Published: 2007-06-04

Total Pages: 394

ISBN-13: 3540714316

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This book constitutes the refereed proceedings of the Third International Workshop on Applied Reconfigurable Computing, ARC 2007, held in Mangaratiba, Brazil, in March 2007. The 27 full papers and 10 short papers presented together with a late-comer contribution from ARC 2006 are organized in topical sections on architectures, mapping techniques and tools, arithmetic, and applications.

Applied Reconfigurable Computing. Architectures, Tools, and Applications

Applied Reconfigurable Computing. Architectures, Tools, and Applications PDF

Author: Steven Derrien

Publisher: Springer Nature

Published: 2021-06-23

Total Pages: 338

ISBN-13: 3030790258

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This book constitutes the proceedings of the 17th International Symposium on Applied Reconfigurable Computing, ARC 2021, held as a virtual event, in June 2021. The 14 full papers and 11 short presentations presented in this volume were carefully reviewed and selected from 40 submissions. The papers cover a broad spectrum of applications of reconfigurable computing, from driving assistance, data and graph processing acceleration, computer security to the societal relevant topic of supporting early diagnosis of Covid infectious conditions.

Computer And Network Technology - Proceedings Of The International Conference On Iccnt 2009

Computer And Network Technology - Proceedings Of The International Conference On Iccnt 2009 PDF

Author: Venkatesh Mahadevan

Publisher: World Scientific

Published: 2009-07-16

Total Pages: 375

ISBN-13: 9814466336

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ICCNT is the main annual computer and network research conference in Chennai that presents cutting edge research work. It will act as a platform for scientists, scholars, engineers and students from universities all around the world to present ongoing research and hence foster better research relations between universities and the computer and networking industry.

Hardware/Software Architectures for Low-Power Embedded Multimedia Systems

Hardware/Software Architectures for Low-Power Embedded Multimedia Systems PDF

Author: Muhammad Shafique

Publisher: Springer Science & Business Media

Published: 2011-07-25

Total Pages: 240

ISBN-13: 1441996923

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This book presents techniques for energy reduction in adaptive embedded multimedia systems, based on dynamically reconfigurable processors. The approach described will enable designers to meet performance/area constraints, while minimizing video quality degradation, under various, run-time scenarios. Emphasis is placed on implementing power/energy reduction at various abstraction levels. To enable this, novel techniques for adaptive energy management at both processor architecture and application architecture levels are presented, such that both hardware and software adapt together, minimizing overall energy consumption under unpredictable, design-/compile-time scenarios.