Lanterna Rally

Author: Tak-Kei Lam

Publisher: John Wiley & Sons

Published: 2016-03-07

Total Pages: 233

ISBN-13: 111875011X

Demonstrates techniques which will allow rewiring rates of over 95%, enabling adoption of deep sub-micron chips for industrial applications Logic synthesis is an essential part of the modern digital IC design process in semi-conductor industry. This book discusses a logic synthesis technique called “rewiring” and its latest technical advancement in term of rewirability. Rewiring technique has surfaced in academic research since 1993 and there is currently no book available on the market which systematically and comprehensively discusses this rewiring technology. The authors cover logic transformation techniques with concentration on rewiring. For many decades, the effect of wiring on logic structures has been ignored due to an ideal view of wires and their negligible role in the circuit performance. However in today’s semiconductor technology wiring is the major player in circuit performance degeneration and logic synthesis engines can be improved to deal with this through wire-based transformations. This book introduces the automatic test pattern generation (ATPG)-based rewiring techniques, which are recently active in the realm of logic synthesis/verification of VLSI/SOC designs. Unique comprehensive coverage of semiconductor rewiring techniques written by leading researchers in the field Provides complete coverage of rewiring from an introductory to intermediate level Rewiring is explained as a flexible technique for Boolean logic synthesis, introducing the concept of Boolean circuit transformation and testing, with examples Readers can directly apply the described techniques to real-world VLSI design issues Focuses on the automatic test pattern generation (ATPG) based rewiring methods although some non-ATPG based rewiring methods such as graph based alternative wiring (GBAW), and “set of pairs of functions to be distinguished” (SPFD) based rewiring are also discussed A valuable resource for researchers and postgraduate students in VLSI and SoC design, as well as digital design engineers, EDA software developers, and design automation experts that specialize in the synthesis and optimization of logical circuits.