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Bio-Inspired Fault-Tolerant Algorithms for Network-on-Chip

Author: Muhammad Athar Javed Sethi

Publisher: CRC Press

Published: 2020-03-17

Total Pages: 212

ISBN-13: 1000048055

Network on Chip (NoC) addresses the communication requirement of different nodes on System on Chip. The bio-inspired algorithms improve the bandwidth utilization, maximize the throughput and reduce the end-to-end latency and inter-flit arrival time. This book exclusively presents in-depth information regarding bio-inspired algorithms solving real world problems focussing on fault-tolerant algorithms inspired by the biological brain and implemented on NoC. It further documents the bio-inspired algorithms in general and more specifically, in the design of NoC. It gives an exhaustive review and analysis of the NoC architectures developed during the last decade according to various parameters. Key Features: Covers bio-inspired solutions pertaining to Network-on-Chip (NoC) design solving real world examples Includes bio-inspired NoC fault-tolerant algorithms with detail coding examples Lists fault-tolerant algorithms with detailed examples Reviews basic concepts of NoC Discusses NoC architectures developed-to-date

Nature-Inspired Networking

Author: Phan Cong-Vinh

Publisher: CRC Press

Published: 2018-02-13

Total Pages: 349

ISBN-13: 1351182064

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"Nature-inspired" includes, roughly speaking, "bio-inspired"+"physical-inspired"+"social-inspired"+ and so on. This book contains highly original contributions about how nature is going to shape networking systems of the future. Hence, it focuses on rigorous approaches and cutting-edge solutions, which encompass three classes of major methods: 1) Those that take inspiration from nature for the development of novel problem solving techniques; 2) Those that are based on the use of networks to synthesize natural phenomena; and 3) Those that employ natural materials to compute or communicate.

Application Specific Integrated Circuits

Author: Edward Fisher

Publisher: BoD – Books on Demand

Published: 2019-04-17

Total Pages: 102

ISBN-13: 178985847X

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The field of application-specific integrated circuits (ASICs) is fast-paced being at the very forefront of modern nanoscale fabrication and presents a deeply engaging career path. ASICs can provide us with high-speed computation in the case of digital circuits. For example, central processing units, graphics processing units, field-programmable gate arrays, and custom-made digital signal processors are examples of ASICs and the transistors they are fabricated from. We can use that same technology complementary metal-oxide semiconductor processes to implement high-precision sensing of or interfacing to the world through analog-to-digital converters, digital-to-analog converters, custom image sensors, and highly integrated micron-scale sensors such as magnetometers, accelerometers, and microelectromechanical machines. ASIC technologies now transitioning toward magneto-resistive and phase-changing materials also offer digital memory capacities that have aided our technological progress. Combining these domains, we have moved toward big data analytics and the new era of artificial intelligence and machine learning. This book provides a small selection of chapters covering aspects of ASIC development and the surrounding business model.

Routing Algorithms in Networks-on-Chip

Author: Maurizio Palesi

Publisher: Springer Science & Business Media

Published: 2013-10-22

Total Pages: 411

ISBN-13: 1461482747

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This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation. Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.

Biologically-Inspired Collaborative Computing

Author: George A. Agoston

Publisher: Springer Science & Business Media

Published: 1979

Total Pages: 250

ISBN-13: 038709654X

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“Look deep into nature and you will understand everything better.” advised Albert Einstein. In recent years, the research communities in Computer Science, Engineering, and other disciplines have taken this message to heart, and a relatively new field of “biologically-inspired computing” has been born. Inspiration is being drawn from nature, from the behaviors of colonies of ants, of swarms of bees and even the human body. This new paradigm in computing takes many simple autonomous objects or agents and lets them jointly perform a complex task, without having the need for centralized control. In this paradigm, these simple objects interact locally with their environment using simple rules. Applications include optimization algorithms, communications networks, scheduling and decision making, supply-chain management, and robotics, to name just a few. There are many disciplines involved in making such systems work: from artificial intelligence to energy aware systems. Often these disciplines have their own field of focus, have their own conferences, or only deal with specialized s- problems (e.g. swarm intelligence, biologically inspired computation, sensor networks). The Second IFIP Conference on Biologically-Inspired Collaborative Computing aims to bridge this separation of the scientific community and bring together researchers in the fields of Organic Computing, Autonomic Computing, Self-Organizing Systems, Pervasive Computing and related areas. We are very pleased to have two very important keynote presentations: Swarm Robotics: The Coordination of Robots via Swarm Intelligence Principles by Marco Dorigo (Université Libre de Bruxelles, Belgium), of which an abstract is included in this volume.

Networks on Chip

Author: Axel Jantsch

Publisher: Springer Science & Business Media

Published: 2007-05-08

Total Pages: 304

ISBN-13: 0306487276

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As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.

Parallel Problem Solving from Nature - PPSN VIII

Author: Xin Yao

Publisher: Springer

Published: 2004-12-16

Total Pages: 1204

ISBN-13: 3540302174

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We are very pleased to present this LNCS volume, the proceedings of the 8th InternationalConferenceonParallelProblemSolvingfromNature(PPSNVIII). PPSN is one of the most respected and highly regarded conference series in evolutionary computation and natural computing/computation. This biennial eventwas?rstheldinDortmundin1990,andtheninBrussels(1992),Jerusalem (1994), Berlin (1996), Amsterdam (1998), Paris (2000), and Granada (2002). PPSN VIII continues to be the conference of choice by researchers all over the world who value its high quality. We received a record 358 paper submissions this year. After an extensive peer review process involving more than 1100 reviews, the programme c- mittee selected the top 119 papers for inclusion in this volume and, of course, for presentation at the conference. This represents an acceptance rate of 33%. Please note that review reports with scores only but no textual comments were not considered in the chairs’ ranking decisions. The papers included in this volume cover a wide range of topics, from e- lutionary computation to swarm intelligence and from bio-inspired computing to real-world applications. They represent some of the latest and best research in evolutionary and natural computation. Following the PPSN tradition, all - persatPPSNVIII werepresentedasposters.Therewere7 sessions:eachsession consisting of around 17 papers. For each session, we covered as wide a range of topics as possible so that participants with di?erent interests would ?nd some relevant papers at every session.

Network-on-Chip Architectures

Author: Chrysostomos Nicopoulos

Publisher: Springer Science & Business Media

Published: 2009-09-18

Total Pages: 237

ISBN-13: 904813031X

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[2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intel’s very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modular approach lies in the substantially reduced Time-To- Market (TTM) incubation period, which is a direct outcome of lower circuit complexity and reduced design effort. The whole system can now be viewed as a diverse collection of pre-existing IP components integrated on a single die.

Asynchronous On-Chip Networks and Fault-Tolerant Techniques

Author: Wei Song

Publisher: CRC Press

Published: 2022-05-10

Total Pages: 381

ISBN-13: 1000578828

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Asynchronous On-Chip Networks and Fault-Tolerant Techniques is the first comprehensive study of fault-tolerance and fault-caused deadlock effects in asynchronous on-chip networks, aiming to overcome these drawbacks and ensure greater reliability of applications. As a promising alternative to the widely used synchronous on-chip networks for multicore processors, asynchronous on-chip networks can be vulnerable to faults even if they can deliver the same performance with much lower energy and area compared with their synchronous counterparts – faults can not only corrupt data transmission but also cause a unique type of deadlock. By adopting a new redundant code along with a dynamic fault detection and recovery scheme, the authors demonstrate that asynchronous on-chip networks can be efficiently hardened to tolerate both transient and permanent faults and overcome fault-caused deadlocks. This book will serve as an essential guide for researchers and students studying interconnection networks, fault-tolerant computing, asynchronous system design, circuit design and on-chip networking, as well as for professionals interested in designing fault-tolerant and high-throughput asynchronous circuits.

Fault Tolerant Computer Architecture

Author: Daniel Sorin

Publisher: Springer Nature

Published: 2022-05-31

Total Pages: 103

ISBN-13: 3031017234

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For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, however, the bounty provided by Moore's law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art - over approximately the past 10 years - in academia and industry. Table of Contents: Introduction / Error Detection / Error Recovery / Diagnosis / Self-Repair / The Future